4-BIT ASYNCHRONOUS (RIPPLE) COUNTER — JK FLIP-FLOPS
TIMING DIAGRAM
CONTROLS
CLOCK CONTROL
SPEED
SLOWFAST
FLIP-FLOP STATES
0
0 0 0 0
FF-D0Q31Q̄3
FF-C0Q21Q̄2
FF-B0Q11Q̄1
FF-A0Q01Q̄0
COUNT SEQUENCE (MOD-16)
CLK
Q3
Q2
Q1
Q0
DEC
Asynchronous (Ripple) Counter: Each JK flip-flop has J=K=1 (Toggle mode). FF-A is clocked by the external CLK. Each subsequent FF is clocked by the complemented output (Q̄) of the previous FF — triggering on the falling edge of Q, which is the rising edge of Q̄. This creates a ripple effect: CLK→Q̄A→Q̄B→Q̄C. Disadvantage: propagation delay accumulates across stages (tpd × N).
4-BIT SYNCHRONOUS COUNTER — JK FLIP-FLOPS
TIMING DIAGRAM
CONTROLS
CLOCK CONTROL
SPEED
SLOWFAST
FLIP-FLOP STATES
0
0 0 0 0
FF-D0Q31Q̄3
FF-C0Q21Q̄2
FF-B0Q11Q̄1
FF-A0Q01Q̄0
COUNT SEQUENCE (MOD-16)
CLK
Q3
Q2
Q1
Q0
DEC
Synchronous Counter: All FFs share the same CLK (no ripple delay). Toggle conditions: JA=KA=1, JB=KB=Q0, JC=KC=Q0·Q1, JD=KD=Q0·Q1·Q2. Each FF toggles only when all lower-order outputs are HIGH — achieved via AND gates. Advantage: no propagation delay; all bits switch simultaneously. Speed = single FF delay regardless of bit-width.
MOD-N COUNTER — NAND GATE RESET FEEDBACK
TIMING DIAGRAM
MOD SELECTOR
SELECT MOD VALUE
CLOCK CONTROL
SPEED
SLOWFAST
CURRENT STATE
0
0 0 0 0
MOD = 5 | RESETS AT 5
Q30
Q20
Q10
Q00
MOD SEQUENCE
CLK
Q3
Q2
Q1
Q0
DEC
Mod-N Counter: A standard counter with NAND-gate feedback on the CLR (Clear) inputs. When the count reaches N, the NAND gate detects specific Q outputs HIGH and immediately forces CLR=0, resetting all FFs. This produces a count of 0 → N-1 → 0. The reset state N appears only as a glitch (very briefly) before being reset. Number of FFs required: n = ⌈log₂(N)⌉.
JK FLIP-FLOP TRUTH TABLE
J
K
CLK
Q (next)
Action
0
0
↑
Q (no change)
HOLD
0
1
↑
0
RESET
1
0
↑
1
SET
1
1
↑
Q̄ (toggle)
TOGGLE
In counters, J=K=1 keeps the FF in Toggle mode — it flips state on every active clock edge.
SYNCHRONOUS COUNTER EXCITATION
FF
J
K
Toggle Condition
FF-A (Q0)
1
1
Always toggles
FF-B (Q1)
Q0
Q0
When Q0=1
FF-C (Q2)
Q0·Q1
Q0·Q1
When Q0=Q1=1
FF-D (Q3)
Q0·Q1·Q2
Q0·Q1·Q2
When Q0=Q1=Q2=1
ASYNC vs SYNC COMPARISON
Feature
Async
Sync
CLK source
Ripple (Q̄→CLK)
Common CLK bus
Propagation delay
N × tpd
1 × tpd
Speed
Slower
Faster
Circuit complexity
Simple
AND gates needed
Glitches
Yes (ripple)
None
Power
Lower
Higher
4-BIT COUNT SEQUENCE
CLK
Q3
Q2
Q1
Q0
DEC
0
0
0
0
0
0
1
0
0
0
1
1
2
0
0
1
0
2
3
0
0
1
1
3
4
0
1
0
0
4
5
0
1
0
1
5
6
0
1
1
0
6
7
0
1
1
1
7
8
1
0
0
0
8
9
1
0
0
1
9
10
1
0
1
0
10
11
1
0
1
1
11
12
1
1
0
0
12
13
1
1
0
1
13
14
1
1
1
0
14
15
1
1
1
1
15
16→0
0
0
0
0
0
MOD-N NAND FEEDBACK
MOD
FFs
NAND Inputs
Reset at
MOD-2
1
Q0
2
MOD-3
2
Q1, Q0
3 (011)
MOD-5
3
Q2, Q0
5 (101)
MOD-6
3
Q2, Q1
6 (110)
MOD-7
3
Q2, Q1, Q0
7 (111)
MOD-10
4
Q3, Q1
10 (1010)
MOD-12
4
Q3, Q2
12 (1100)
Design rule: Identify the binary representation of N. Apply NAND to the bits that are 1 in that representation. Output of NAND drives the active-low CLR of all FFs.